The invention relates to a semiconductor memory comprising non-volatile memory cells which are electrically programmable and erasable by means of tunnel currents (EEPROM) and which are arranged in memory cell groups of n lines and m columns each, and comprising memory cells formed in a semiconductor body with source and drain zones and a channel formed between these zones and covered by a gate oxide, a floating gate extending over the gate oxide, and a control gate extending over the floating gate and separated therefrom by a thin dielectric, thus forming a floating-gate transistor, the gate oxide and the thin dielectric being so chosen that electrons can flow towards or from the floating gate owing to Fowler-Nordheim tunnelling current, while the memory cell groups are so formed that the sources and drains of n cells are connected in series and this serial connection forms the bit line for the columns of a cell block, and that the control gate is common to m memory cells of a line of the cell block lying next to one another and forms the word line for the line of the memory cell group.
The invention also relates to a method of operating such a semiconductor memory.
A semiconductor memory of this kind is known from IEEE Journ. of Solid-State-Circuits 24 (1989) 5, 1238-1243. In this known semiconductor memory, problems of over-erasing of memory cells can arise in the case of short access times, which problems are usually solved through the introduction of an additional access transistor. This involves, however, a considerable increase in the surface area of the memory.